Gate driver for thyristor

ABSTRACT

A predetermined signal pattern is generated to produce current for driving the GCT thyristor. The current is produced by the use of a down converter. Also, a current limiter having an FET is used for protecting the down converter from being damaged by a negative voltage appearing at the gate of GCT when the GCT thyristor receives reverse direction load current.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a gate driver for driving athyristor, such as a GCT (gate commutated turn-off) thyristor, a GTO(gate turn-off) thyristor, a static inductive thyristor (SITH), or apower transistor, in a stable condition.

[0003] 2. Prior Art

[0004] GCT On-State Gate Current Requirements

[0005] GCT and GTO have similar turn-on and on-state gate currentrequirements. The gate driver provides a turn-on pulse with high dl/dtand peak current, and thereafter provides a steady state DC on-statesustaining current. The gate driver sometimes receives negative gatevoltage during on-state of the GCT/GTO.

[0006] A new situation, unlike in the case of the GTO, is introduced fordriving the GCT. The gate drivers for the GCT has its feature in theamount of turn-on peak current and its shape. The turn-on currentincrease (dl/dt) for GCT is 10 times to 50 times higher than that oftypical GTOs, and trigger peak currents also are selected 5 to 10 timeshigher in order to reduce turn-on loss. A 6 inch GCT thus may requiredl/dt=500A/us and a peak current of 300A.

[0007] While such a sharp high pulse safely turns on the GCTaccompanying a high rate of rise of anode current, a long pulse durationmust be provided after the sharp high pulse to maintain the GCT inon-state, if GCT operation accompanies a small rate of rise of anodecurrent. Thereafter, on-state gate current similar to the GTO's(approximately 10A for a 4 inch or 6 inch device) is to be applied.

[0008] If no protection circuit, such as a current limiter, is provided,the gate driver may be damaged when the GCT's or GTO's load currentchanges its flow direction from a forward direction to a reversedirection. The load current flows in the reverse direction, the loadcurrent will flow through a freewheel diode provided in parallel to theGCT. Thus, the GCT's anode turns negative with respect to its cathode. Aparasitic diode in the GCT allows a negative potential to appear at thegate of the GCT.

[0009] Thereafter when the load current changes its flow direction againfrom the reverse direction to the forward direction, the load currentmay flow again through the GCT. Then, a safe GCT on-condition has to beestablished again.

[0010] Basically such requirements also are well known from GTOoperation. GCT circuits are designed for higher switching frequency,and, as a consequence, freewheel diodes must respond to a considerablyhigh forward voltage drop, resulting in GCT gate voltage as low as −5Vduring normal converter operation.

[0011] Prior Art Circuits

[0012] The peak current is created from a voltage source by resistor andcapacitor circuit. In order to produce a high shooting pulse with asteep and rapid rising (dl/dt=500A/us), and a relatively long down slopepulse (10us to 40us) after the shooting pulse require several RCcombinations with complicated adjustments. In such a design the totalloss may exceed 50W for a 6 inch GCT drive.

[0013] A German Patent Laid-open publication No. DE3709150 and a PCTInternational Publication No. WO9407309 disclose the GTO driver usingswitched current sources. Inductors are fed to create the sources, andexcessive energy is fed back to the power supply.

[0014] Basically in such way, very low loss can be achieved. But fourhigh current switching devices and three diodes are required forgenerating a turn-on pulse and an on-state current. And the highturn-off peak current has to pass through a series connection of aswitching element and an additional diode. Such a circuit cannot be usedfor a gate driver of GCT.

[0015] U.S. Pat. No. 4,791,350 discloses a gate driver which uses aswitch-mode step down current regulator as a source for the GTO's steadystate gate current. The regulator incorporates a switch and a freewheeldiode, it's output is directly coupled to the GTO's gate, and a highcurrent pulse is generated by a separate circuit having a switch and aresistor.

[0016] In this way U.S. Pat. No. 4,791,350 suggests to reduce gatedriver losses. But if a negative GCT gate voltage should appear, theregulator's output current will increase without control. Moreoverconsiderable losses are generated in the regulator's freewheel diode,when gate currents exceeding 5A are required. Also, high losses willresult from the high current pulse resistor.

[0017] Japanese Patent laid-open publication No. H3-97315 and EP Patentpublication No. 0 416 933 discloses a circuit to solve the problem withnegative gate potential. The freewheel diode is connected to thenegative supply line. The inductor is charged by the positive supplysource. Upon freewheel, the charge in the inductor will be discharged tothe negative supply. In this way the circuit can operate stable underall positive and negative GTO gate voltage conditions.

[0018] Such circuit is applicable for the generation of a small gatecurrent. With high gate current, however, a lot of energy is transferredfrom the positive supply source to the negative supply source, and itmust be transferred back to the positive supply by an appropriate powerreturning circuit. In the case of GCT, for example, a gate current Igmay be about 10A and a gate voltage Vg is about-20V. Then, a circulatingpower would be approximately 200W. In contrast to this, the active gatepower according to this reference may be as small as Vg×lg=0.6V×10A=6W.As a result tremendous over design of gate current generator and powersupply is required, and considerable amount of loss (approximately20W-40W) is generated even with high performance switch-mode circuits.

[0019] EP Patent publication 893883 discloses a gate driver whichhandles the GCT's freewheel situation in another way. A bipolartransistor, implemented as emitter follower, is to limit the GCT's gatecurrent at negative gate voltage. The current is generated from voltagepulses with high efficiency.

[0020] For gate current Ig up to 2A, a circuit can be designed withappropriate components. At a higher gate current, the bipolar transistorgain will decrease below 20. Then, high base current is required, andloss will increase due to higher VCEsat (saturation of voltage Vce). Atlg=10A, lb greater than 0.5A will be required, and VCEsat will amount toapproximately 1V with the known PNP transistors.

[0021] Moreover, a high base current must be maintained with a GCT gatevoltage being maintained not lower than 0.4V. Then, for higher GCT gatevoltage and for open circuit condition (no GCT installed), a severetrade-off must be handled, complicating design and limiting theperformance of the gate driver.

SUMMARY OF THE INVENTION

[0022] A circuit must be found which is appropriate to realize highcurrent GCT drive. It has to generate a sharp, high trigger currentpulse for GCT turn-on, a long trigger current tail and high gate currentwith low loss, and it has to be safe under all gate voltage operatingconditions.

[0023] Moreover the circuit has to be such that it can be realizedmainly with SMD components and technology in order to allow very compactand cost effective solutions.

[0024] Claim 1 of the invention claims a gate driver for driving athyristor (8) having an anode, a cathode and a gate by providing a gatecurrent to the gate of said thyristor during an on-command signal ispresent, said gate driver comprising:

[0025] a turn-on pulse generator (2) for generating a turn-on pulse inresponse to a leading edge of said on-command signal;

[0026] a down converter (3) for producing a down slope currentimmediately following said firing pulse; and

[0027] a current limiter (4) having a MOSFET (403) connected to the gateof said thyristor for supplying current from said down converter to thegate of said thyristor, said current limiter monitoring the gate voltageat the gate of said thyristor and increasing an internal resistance ofsaid MOSFET relatively to the negative voltage increase of said gatevoltage.

[0028] Claim 2 claims a gate driver according to claim 1, wherein saiddown converter comprises:

[0029] a pattern generator (310) for generating a pattern of a currentto be produced from said down converter;

[0030] a conduction pulse generator (311) for generating conductionpulses in accordance with said pattern;

[0031] a switching element (312) for conducting a current from a powersource (7) in response to said conduction pulses and producing a pulsecurrent; and

[0032] an inductor (314) for smoothing said pulse current;

[0033] said pattern generator generating a pattern having a rising edgeand down slope portion after the rising edge, so that said down slopecurrent produced from said down converter decreases relatively to saidpattern.

[0034] Claim 3 claims a gate driver according to claim 2, wherein saiddown converter further comprises:

[0035] another conduction pulse generator (321) for generating anotherconduction pulses in accordance with said pattern;

[0036] another switching element (322) for conducting a current fromsaid power source (7) in response to said another conduction pulses andproducing another pulse current; and

[0037] another inductor (324) for smoothing said another pulse currentso that said down slope current is increased.

[0038] Claim 4 claims a gate driver according to claim 2, wherein saiddown converter further comprises:

[0039] additional inductor (344) provided in parallel to said inductor(314); and

[0040] additional switching element (347) provided in series to saidadditional inductor (344) to produce a greater down slope current.

[0041] Claim 5 claims a gate driver according to claim 2, wherein saiddown converter further comprises:

[0042] additional inductor (344) provided in parallel to said inductor(314); and

[0043] a saturating reactor element (356) provided in series to saidadditional inductor (344) to produce a greater down slope current.

[0044] Claim 6 claims a gate driver according to claim 1, wherein saidcurrent limiter comprises:

[0045] a comparator for comparing an output voltage (V3) at the outputof said down converter with a predetermined voltage (V401) and producingan adjust signal relative to a difference between said output voltage(V3) and said predetermined voltage (V401) when said output voltage (V3)falls below said predetermined voltage (V401),

[0046] said MOSFET (403) receiving said adjust signal to change itsinternal resistance relatively to said adjust signal.

[0047] Claim 7 claims a gate driver according to claim 6, wherein saidcomparator comprises an operational amplifier (402).

[0048] Claim 8 claims a gate driver according to claim 6, wherein saidcomparator comprises bipolar transistors (412, 415, 416).

[0049] Claim 9 claims a gate driver according to claim 6, wherein saidcurrent limiter further comprises a freewheel diode connected parallelto said MOSFET.

[0050] Claim 10 claims a gate driver according to claim 1, wherein saidturn-on pulse generator (1) comprises a capacitor (205), a diode (206)connected parallel to said capacitor, a switching element (202) and areactor (204) to produce a sharp high pulse.

[0051] Claim 11 claims a gate driver according to claim 1, furthercomprising a bias current generator to provide a low level bias currentto said gate of the thyristor.

[0052] Claim 12 claims a gate driver according to claim 1, wherein saidthyristor (8) is a GCT.

BRIEF DESCRIPTION OF THE DRAWINGS

[0053]FIG. 1 is a block diagram of a gate driver for a thyristor.

[0054]FIG. 2 is a waveforms observed at major points in the blockdiagram of FIG. 1.

[0055]FIG. 3 is a circuit diagram of a turn-on pulse generator shown inFIG. 1.

[0056]FIG. 4 is a circuit diagram of a down converter and currentlimiter shown in FIG. 1.

[0057]FIG. 5 is a waveforms observed at major points in the circuit ofFIG. 4.

[0058]FIG. 6 is a waveforms observed in the down converter of FIG. 4.

[0059]FIG. 7 is a circuit diagram of a bias current generator shown inFIG. 1.

[0060]FIG. 8 is a circuit diagram according to the first modification.

[0061]FIG. 9 is a waveforms observed in the circuit of FIG. 8.

[0062]FIG. 10 is a circuit diagram according to the second modification.

[0063]FIG. 11 is a waveforms observed in the circuit of FIG. 10.

[0064]FIG. 12 is a circuit diagram according to the third modification.

[0065]FIG. 13 is a circuit diagram according to the fourth modification.

[0066]FIG. 14 is a circuit diagram according to the fifth modification.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0067] Referring to FIG. 1, a block diagram of a gate driver accordingto the present invention is shown for driving a large capacity switchingelement 8 into ON and OFF conditions. The gate driver of the presentinvention can be applied to various types of switching element 8, forexample, a GCT (gate commutated turn-off) thyristor, a GTO (gateturn-off) thyristor, a static inductive thyristor (SITH), or a powertransistor. The present invention is, however, particularly suitable foruse with a GCT thyristor. Thyristor 8 has an anode, a cathode and agate. Thyristor 8 is connected in parallel with a diode 81 in reversedirection such that anode and cathode of tyristor 8 are respectivelyconnected to cathode and anode of diode 81. Thyristor 8 is furtherconnected with a load (not shown) in series.

[0068] In FIG. 1, a reference number 1 is a turn-off pulse generator forgenerating a turn-off pulse lg3, 2 is a turn-on pulse generator forproducing a turn-on pulse or firing pulse lg1, 3 is a down converter, 4is a current limiter, 5 is a bias current generator for generating abias current lg4 and 9 is a controller for producing an on-commandsignal S1. Current limiter 4 operates in association with down converter3 and produces a sustaining current lg2. The currents lg1, lg2, lg3 andlg4 are added together to form a gate current lg.

[0069]FIG. 2 shows waveforms observed at major points in the circuit ofgate driver of FIG. 1. Particularly, FIG. 2(a) shows a voltage Vakacross thyristor 8 between anode and cathode, FIG. 2(b) shows an anodecurrent la through thyristor 8, FIG. 2(c) shows a gate current Ig to thegate of thyristor 8, FIG. 2(d) shows a gate voltage Vg at the gate ofthyristor 8 and FIG. 2(e) shows an on-command-signal S1 produced fromcontroller 9.

[0070] As shown in FIG. 2(e) the controller 9 produces a high levelon-command-signal S1 in a period 102-109 for activating the gate driverso as to turn on the thyristor 8 in said period 102-109.

[0071] As shown in FIG. 2(c), in response to the leading edge or risingedge of the on-command-signal S1 at time 102, the turn-on pulsegenerator 2 is activated to produce an instantaneous high level current(a firing pulse) lg1 in a period 102-103 which is, e.g., 5-30microseconds. A peak current value of the firing pulse lg1 is e.g.,several hundreds to 1000 amperes. The firing pulse lg1 is applied to thegate of the thyristor 8 at a very beginning of the gate current lg toturn on the thyristor 8.

[0072] Also, as shown in FIG. 2(c), in response to the leading edge ofthe on-command-signal S1, the down converter 3 produces a down slopecurrent lg2 as a leading portion of the sustaining current lg2. The downslope current lg2 is produced in a period 102-104 which is e.g., 10-100microseconds. The down slope current has a rising edge at time 102 and adown slope portion in a period 102-104. The rising edge is overlappedwithin the firing pulse. It is possible, however, that the down slopecurrent has its rising edge at time 103. In this case, the down slopeportion exists in time 103-104. The down slope current is provided toensure that the thyristor 8 maintains its on state even after the firingpulse (time 102-103) disappears.

[0073] In response to the leading edge of the on-command-signal S1, thebias current generator 5 produces a bias current lg4, which is e.g.,several hundreds milliamperes during a period 102-109. In FIG. 2(c), thebias current lg4 is not shown, because it is very small compared tosustaining current lg2.

[0074] As shown in FIG. 2(b), when the anode current la suddenly fallsto a negative value at time 105 due to some sudden change in the loadconnected to the thyristor 8, a reverse anode current la flows throughdiode 81, and at the same time the gate voltage Vg falls below zero. Thecurrent limiter 4 is provided to control the gate current lg applied tothe gate of the thyristor 8 to stay in the forward bias current evenwhen the gate voltage Vg falls below zero.

[0075] Each of the circuits 1-5 will be described in detail below.

[0076] Referring to FIG. 3, turn-on pulse generator 2 is shown. Theturn-on pulse generator 2 comprises a trigger pulse generator 201, aswitching transistor 202, a freewheel diode 203, a pulse forming reactor204, a pulse capacitor 205, a capacitor freewheel diode 206, a reactor207 and a diode 208.

[0077] Operation of the turn-on pulse generator 2 is as follows.

[0078] First, capacitor 205 is charged to a preset voltage 2Vb by acharging circuit from a power source 7 having a voltage Vb, throughreactor 207 and diode 208. At time 102, in response to the leading edgeof the on-command-signal S1 from controller 9, the trigger pulsegenerator 201, having a pulse generator, such as a data flip-flop,produces a trigger pulse having a predetermined pulse width. The triggerpulse is applied to transistor 202. Thus, at time 102, transistor 202turns on. Then, capacitor 205 is connected to reactor 204, and a gatepulse current lg1 starts to flow into the gate of the thyristor 8. Asthe gate pulse current lg1 increases, voltage of capacitor 205 willdecrease. When the voltage of capacitor 205 reaches zero, the gate pulsecurrent reaches a maximum level. Therefore, capacitor 205 and reactor204 are selected to perform a resonant operation such that startingdl/dt and peak current of the gate pulse current satisfy therequirements of the thyristor 8. Thus, during the discharge of capacitor205, the gate pulse current lg1 flows along a line A1 shown in FIG. 3

[0079] When the voltage across the capacitor 5 turns negative, thendiode 206 will conduct to allow a by-pass current A2 shown by a dottedline, and the resonant operation stops. As a consequence, using theby-pass current A2, the current in reactor 204 is kept at the highlevel. Then, the current A1 decreases slowly due to the voltage at thegate of thyristor 8, and also due to the losses in the reactor 204,switching transistor 202 and diode 206.

[0080] After a predetermined time, trigger pulse generator 201terminates to generate the trigger pulse, thus, turning off switchingtransistor 202. Then the reactor current commutate along line A3, sothat the energy stored in reactor 204 is released through the freewheeldiode 203 into a negative supply.

[0081] An operation under the presence of a negative gate bias voltageis very similar to the above operation.

[0082] Upon triggering of transistor 202 by the trigger pulse generator201, the capacitor 205 discharges, and reactor 204 cumulates energy.Then freewheel diode 206 conducts after the capacitor 205 is dischargedto zero volts. Depending on the amount of negative gate bias voltage,the gate current will decrease slowly or increase with time. At time 103transistor 202 is turned off, and the energy in reactor 204 is releasedinto power supply 6.

[0083] With small negative bias voltage, safe operation of the circuitcan be achieved. If high negative bias voltage must be handled like in acase of a fast high voltage GCT freewheel diode, then the gate currentmay reach excessively high current even within the short period of time(102-103). In such a case, the gate drive voltage to transistor 202 andits characteristics is selected to limit such current. As a consequence,safe operation is achieved even under high negative bias voltage.

[0084] Referring to FIG. 4, down converter 3 and current limiter 4 areshown. First, the down converter 3 is described.

[0085] Down converter 3 has a pattern generator 310, a conduction pulsegenerator 311, an FET 312, a low loss Schottky diode 313, an inductor314 a current sense resistor 315, and a diode 316. Conduction pulsegenerator 311, FET 312, low loss Schottky diode 313, inductor 314 andcurrent sense resistor 315 are connected to form a low loss step downconverter.

[0086] In response to the on-command signal from controller 9, patterngenerator generates a pattern signal S2, and produces an up limit signalS2-up and a low limit signal S2-low, as shown in FIG. 5(d). The patternsignal S2 has a rising edge at time 102, a down slope portion duringtime 102-104 and a constant level during time 104-109. The up limitsignal S2-up and low limit signal S2-low are applied to conduction pulsegenerator 311 which generates a conduction pulse shown in FIG. 6(a) in amanner described below.

[0087] Conduction pulse generator 311 detects a current flowing throughresistor 315, and compares the current level with the up limit signalS2-up and low limit signal S2-low. When current l315 falls below the lowlimit signal S2-low, the conduction pulse generator 311 produces aconduction pulse (FIG. 6(a)) to drive FET 312 into conducting state. Inthis way the current from source 7 is applied through a seriesconnection of inductor 314, resistor 315, FET 403 and to the gate of thethyristor 8. The current conducted through FET 403 is a pulse current,but is smoothed after inductor 314. As a consequence, induction voltageV314 is set positive, and current l315 increases with a rate of risegiven by V314 and the inductance of inductor 314.

[0088] Thereafter, as shown in FIG. 6(b), when current l315 increases tothe up limit signal S2-up, the conduction pulse generator 311 terminatesthe conduction pulse so as to switch FET 312 into blocking state. Thecurrent l315 commutates to diode 313. The voltage V314 is reversed andcan be expressed as follows:

V314=−(V3+V313+R315×l315)

[0089] wherein V3 is an output voltage of the down converter 3. Then,current l 315 decreases again towards the low limit signal S2-low.

[0090] The voltage of source 7 is selected considerably higher than Vg.In this way high rate of rise of current l315 (dl315/dt) is achieved atconduction of FET 312, and small dl315/dt results at conduction of diode313, resulting in long conduction of diode 313 and short conduction ofFET 312. As a consequence the average current drawn from source 7 issmall compared to l315, and voltage 7 can be generated with standard lowpower components.

[0091] Diode 313 and FET 403 are selected for low on-state resistance(RDSon). In this way V313 and V403 become smaller than Vg, and withsimilar selection of resistor 315, a total efficiency in the order of50% is achieved even at Vg=0.6V and l315=10A. Thus, a current producedfrom the down converter 3 decreases immediately after the firing pulsebut gradually.

[0092] Inductor 314 is selected for high saturation current. Then, dueto the characteristics of the FETs and the diode, a high level currentcan be generated and supplied to the gate of the thyristor 8 for aperiod of time 103-104. To achieve this, the pattern generator 310increases the up and low limit signals S2-up and S2-low. In this way thelong slope pulse (time 103-104) also is generated with high efficiency.The long slope pulse is explained as produced during time 103-104, butcan be produced during time 102-104, partly overlapping with the firingpulse (time 102-103).

[0093] Still referring to FIG. 4, the current limiter 4 is describednext.

[0094] Current limiter 4 has a constant voltage source 401, a comparator402 formed by an operational amplifier, and a p-channel FET 403. When agate voltage Vg is pulled negative by a negative anode voltage (time105-106), the output voltage V3 of down converter 3 also decreases.Comparator 402 detects the gate voltage Vg by comparing the downconverter's output voltage V3 with a predetermined constant voltageV401. When the gate voltage Vg decreases to and below the constantvoltage V401, comparator 402 produces an adjust signal having a levelproportional to the decreased level of down converter output voltagebelow the constant voltage V401. The adjust signal is applied to thegate of FET 403, which thereupon starts to increase the internalresistance, resulting such that the voltage drop across the FET 403increases. Thus, the voltage of the output side (the side connected tothe gate of the thyristor 8) of the FET is reduced and the input sidethereof is maintained nearly the same. Thus, the voltage drop observedat the gate of thyristor 8 is mainly absorbed in the voltage dropeffected across FET 403, so that the voltage V3 applied to the inputside of the FET 403 will be maintained in the positive region, as shownin FIG. 5(b) even when the gate voltage Vg falls below zero. Thus, thelow loss step down converter will continue to operate with normaloperating conditions.

[0095] As apparent from the above, the current limiter 4 monitors thegate voltage Vg at the gate of thyristor 8 and maintains the forwardbias current to the gate of the thyristor 8 even when the gate voltagefalls less than zero volt. By limiter 4, the thyristor 8 can bemaintained in the on-state even when a sudden current drop appears inthe anode current la. Also, by limiter 4, the gate current lg can bemaintained in the forward bias current, eventually protecting variouscircuits in the gate driver, particularly the circuit in the downconverter from receiving a reverse bias current.

[0096] It is to be noted that down slope current may be producedimmediately after the comparator 402 stops generating the high levelsignal, i.e., at time 106 when the gate voltage Vg changes from thenegative to positive. For this purpose, an output of comparator 402 canbe also applied to the pattern generator 310.

[0097] Negative gate voltage as low as −5V like in the case of a fastfreewheel diode will produce high loss in the limiter. Then, by anadditional connection to the gate voltage, pattern generator 310 may beactivated to reduce pattern signal S2 during such time. As shown in FIG.2(c), this will result in reduced gate current inside the intervalbetween 105 and 106 and considerable reduction of loss in MOSFET 403.

[0098] Setting such a low current by down converter 3 requires very highprecision in the sense amplifier of conduction pulse generator 311.Therefore a bias generator is included in the gate drive circuit. Then,output current of down converter 3 is set to zero by pattern generator310 at a pre-set low gate voltage, e.g. at −2V, and gate bias current ismaintained by the bias generator.

[0099] Referring to FIG. 7, a bias current generator 5 is shown. Thebias current generator 5 has a pulse generator 501, a switchingtransistor 502, a diode 503, a reactor 504 and a resistor 505. The pulsegenerator 501 produces a pulse at time 102 in response to the leadingedge or rising edge of on-command signal S1 produced from the controller9. Thus, in response to the pulse from the pulse generator 501,switching transistor 502 turns on to produce a positive going pulsewhich is applied through reactor 504 and resistor 505 to the gate ofthyristor 8. The freewheel diode 503 is connected to the negativepotential of source 6. As a consequence the bias current generator willmaintain normal operation also at gate voltage as low as the output ofsource 6.

[0100] Modification 1

[0101] Referring to FIG. 8, a first modification is shown. The downconverter 3 is modified. The down converter 3 has a pattern generator310, a first converter 3 a and a second converter 3 b. The firstconverter 3 a has a conduction pulse generator 311, FETs 312 and 317, aninductor 314, a resistor 315, and a diode 316. Similarly, the secondconverter 3 b has a conduction pulse generator 321, FETs 322 and 323, aninductor 324 and a resistor 325.

[0102] The pattern generator 310 produces up limit signal S2-up and alow limit signal S2-down in a manner similar to that described above.

[0103] It is noted that the inductor 324 has an inductance which isequal to a half of the inductance of the inductor 314. The conductionpulse generator 321 is operative only during the down slope period (time102-104), and the conduction pulse generator 311 is operative during theentire on-period (time 102-109). Other than inductor, diode 316 andconduction pulse generator 321, the circuit elements in the firstconverter 3 a are the same as those in the second converter 3 b.

[0104] Thus, as shown in FIG. 9(a), the first converter 3 a produces acurrent shown by a portion A, and the second converter 3 b produces acurrent shown by a portion B. Since reactor 324 has a reactance (½)L andreactor 314 has a reactance L, the current in portion B is twice asgreat as the current in portion A. By the circuit of FIG. 8 a tripplehigh slope pulse (time 103-104) including current portions A and B canbe produced with high efficiency.

[0105] Modification 2

[0106] Referring to FIG. 10, a second modification is shown. The downconverter 3 is modified. When compared with the down converter 3 shownin FIG. 4, the down converter 3 shown in FIG. 10 has an FET transistor319 in place of diode 313. Other arrangements are the same as thoseshown in FIG. 4. As shown in FIG. 11, a signal applied to the gate ofFET 319 has a phase opposite to that of the signal applied to the gateof FET 312. In this modification, a synchronous rectifier (FETs 312 and319) is implemented to generate long slope pulse current (time 103-104).Upon selection of low on-state (RDSon) for FET 319, voltage V319obtained across the FET 319 is by far smaller than the voltage obtainedacross the diode 313 of FIG. 4 (V319<<V313). Thus, efficiency forobtaining long slope pulse clearly exceeding 50% is achieved.

[0107] Modification 3

[0108] Referring to FIG. 12, a third modification is shown. The downconverter 3 is modified. When compared with the down converter shown inFIG. 10, the down converter shown in FIG. 12 further has a reactor 344,a resistor 345, a diode 346 and a FET 347. The gate of FET 347 isconnected to the pattern generator 310. The FET 347 is controlled by acontrol pulse from the pattern generator 310 to conduct only during theslope period (time 102-104 or 103-104).

[0109] In the modification shown in FIG. 12, only one synchronousrectifier circuit (311, 312, 319) is provided to generate a double longslope pulse (time 103-104) including current portions A and B shown inFIG. 9. The current portion B is generated by the circuit elements 344,345, 346 and 347, and the rectifier circuit (311, 312, 319) is used incommon for generating the portions A and B. Reactor 344 has a reactance(½)L and reactor 314 has a reactance L. The generation of the currentportion B is explained below.

[0110] At time 103 FET 347 is conducted by pattern generator 310. Sincea series connection of reactor 344 and resistor 345 is connected inparallel to a series connection of reactor 314 and sense resistor 315,additional current will flow through the series connection of reactor344 and resistor 345. Thus, the down slope current increases.

[0111] At time 104 the down slope current reaches to the stable biascurrent. Thus, the pattern generator 310 terminates to produce thecontrol pulse Then, FET 347 is turned off. Through diode 346 the energystored in reactor 344 is released to the positive supply 7, and thestable bias current supply continues by reactor 314 and sense resistor315.

[0112] Modification 4

[0113] Referring to FIG. 13, a fourth modification is shown. The downconverter 3 is modified. The down converter shown in FIG. 13 is verysimilar to the down converter shown in FIG. 12. In place of FET 347 inFIG. 12, a saturating reactor 356 is provided. Also, the diode 346 isremoved in FIG. 13. Other circuit elements are the same as those shownin FIG. 12. The operation is as follows.

[0114] At time 102 the pattern generator 310 produces a high patternsignal S2 so as to build up a high DC current through reactor 314 andreactor 344. Then reactor 356 saturates by the DC current throughreactor 344. Reactor 356 has a feature to present a small saturationinductance value, so that the energy is mainly accumulated in reactors344 and 314. As a consequence, a high amount of current is produced byelements 344, 345 and 356.

[0115] At time 104 the pattern generator 310 terminates to produce ahigh pattern signal. Reactor 356 is designed to go out of saturationunder such condition. Then, reactor 356 has a feature to present a highinductance value, so a small amount of current flows through elements344, 345 and 356. In such way low loss in the sense resistor 315 duringgeneration of long slope pulse and high precision of lg2 can beachieved.

[0116] Modification 5

[0117] Referring to FIG. 14, a fifth modification is shown. The currentlimiter 4 is modified. When compared with the current limiter 4 shown inFIG. 4, the comparator 402 is replaced with three bipolar transistors412, 415 and 416 and resistors 413 and 414. Other circuit elements inthe current limiter 4 of FIG. 14 are the same as those in the currentlimiter of FIG. 4. Operation is as follows.

[0118] Transistor 412 compares it's base-emitter threshold value with avoltage difference between a constant voltage V401 and input voltage V3,and controls the voltage across resistor 414. When the voltage at thebase of transistor 412 drops, transistor 412 becomes more conductive toincrease the voltage at the base of transistor 416, and eventuallyincreasing the voltage at the emitter of transistor 416. The voltage atthe emitter of transistor 416 serves as the adjust signal for adjustingthe internal resistance of FET 403. When the adjust signal increases,FET 403 starts to increase the internal resistance, resulting inblocking of the voltage drop at the gate of thyristor 8 in a mannerdescribed above in connection with FIG. 4. In this way a very small andcost effective current limiter is realised.

[0119] Effect of the invention

[0120] The gate driver according to claim 1 of the present inventionrealises a low loss small size circuit for high power GCT or RGCT. Theuse of the pattern generator and switching elements enable a low losscircuit, creating the long high down slope current. Also, no componentthat takes a high loss is used. One or more MOSFET(s) in the maincurrent path in the current limiter protects circuit components in thedown converter.

[0121] According to claim 2, the loss in the down converter is reducedby introducing a controlled MOSFET instead of conventional diodes.

[0122] According to claim 3, the loss in the down converter is reducedduring high down slope current generation by another generation elementsoptimised for the generation of such current.

[0123] According to claim 4, a number of circuit elements can bereduced.

[0124] According to claim 5, a number of circuit elements can bereduced, with a simple circuit.

[0125] According to claim 6, current limiter protects circuit elementsin the down converter particularly during negative GCT gate bias. Also atransition between operations under positive and negative gate bias canbe carried out smoothly.

[0126] According to claim 7, the current limiter can be arranged withsimple circuit and low cost using a high bandwidth power operationalamplifier.

[0127] According to claim 8, the current limiter can be arranged withsimple circuit and low cost using a high bandwidth transistors.

[0128] According to claim 9, gate current of the thyristor can becontrolled throughout the full range of negative gate voltage with verylow loss.

[0129] According to claim 10, the turn-on pulse can be generated withsimple and small circuit elements. Thus low loss and full protectionagainst negative gate bias can be realized.

[0130] According to claim 11, the gate current can be controlled in thefull negative gate bias range with low loss even with high gate current.

[0131] According to claim 12, the switching of a high load current canbe accomplished rapidly and steadily.

What is claimed is:
 1. Gate driver for driving a thyristor having ananode, a cathode and a gate by providing a gate current to the gate ofsaid thyristor during an on-command signal is present, said gate drivercomprising: a turn-on pulse generator for generating a turn-on pulse inresponse to a leading edge of said on-command signal; a down converterfor producing a down slope current immediately following said firingpulse; and a current limiter having a MOSFET connected to the gate ofsaid thyristor for supplying current from said down converter to thegate of said thyristor, said current limiter monitoring the gate voltageat the gate of said thyristor and increasing an internal resistance ofsaid MOSFET relatively to the negative voltage increase of said gatevoltage.
 2. Gate driver according to claim 1, wherein said downconverter comprises: a pattern generator for generating a pattern of acurrent to be produced from said down converter; a conduction pulsegenerator for generating conduction pulses in accordance with saidpattern; a switching element for conducting a current from a powersource in response to said conduction pulses and producing a pulsecurrent; and an inductor for smoothing said pulse current; said patterngenerator generating a pattern having a rising edge and down slopeportion after the rising edge, so that said down slope current producedfrom said down converter decreases relatively to said pattern.
 3. Gatedriver according to claim 2, wherein said down converter furthercomprises: another conduction pulse generator for generating anotherconduction pulses in accordance with said pattern; another switchingelement for conducting a current from said power source in response tosaid another conduction pulses and producing another pulse current; andanother inductor for smoothing said another pulse current so that saiddown slope current is increased.
 4. Gate driver according to claim 2,wherein said down converter further comprises: additional inductorprovided in parallel to said inductor; and additional switching elementprovided in series to said additional inductor to produce a greater downslope current.
 5. Gate driver according to claim 2, wherein said downconverter further comprises: additional inductor provided in parallel tosaid inductor; and a saturating reactor element provided in series tosaid additional inductor to produce a greater down slope current. 6.Gate driver according to claim 1, wherein said current limitercomprises: a comparator for comparing an output voltage at the output ofsaid down converter with a predetermined voltage and producing an adjustsignal relative to a difference between said output voltage and saidpredetermined voltage when said output voltage falls below saidpredetermined voltage, said MOSFET receiving said adjust signal tochange its internal resistance relatively to said adjust signal.
 7. Gatedriver according to claim 6, wherein said comparator comprises anoperational amplifier.
 8. Gate driver according to claim 6, wherein saidcomparator comprises bipolar transistors.
 9. Gate driver according toclaim 6, wherein said current limiter further comprises a freewheeldiode connected parallel to said MOSFET.
 10. Gate driver according toclaim 1, wherein said turn-on pulse generator comprises a capacitor, adiode connected parallel to said capacitor, a switching element and areactor to produce a sharp high pulse.
 11. Gate driver according toclaim 1, further comprising a bias current generator to provide a lowlevel bias current to said gate of the thyristor.
 12. Gate driveraccording to claim 1, wherein said thyristor (8) is a GCT.